Integrated circuits (ICs), such as ultra-large-scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). Such transistors can include semiconductor gates disposed above a channel region and between source and drain regions. The source and drain regions are typically heavily doped with a P-type dopant (e.g., boron) or an N-type dopant (e.g., phosphorous).
Double gate transistors, such as vertical double gate silicon-on-insulator (SOI) transistors or finFETS, have significant advantages related to high drive current and high immunity to short channel effects. An article by Huang, et al. entitled “Sub-50 nm FinFET: PMOS” (1999 IEDM) discusses a silicon transistor in which the active layer is surrounded by a gate on two sides. However, double gate structures can be difficult to manufacture using conventional IC fabrication tools and techniques. Further, patterning can be difficult because of the topography associated with a silicon fin. At small critical dimensions, patterning may be impossible.
By way of example, a fin structure can be located over a layer of silicon dioxide, thereby achieving an SOI structure. Conventional finFET SOI devices have been found to have a number of advantages over devices formed using semiconductor substrate construction, including better isolation between devices, reduced leakage current, reduced latch-up between CMOS elements, reduced chip capacitance, and reduction or elimination of short channel coupling between source and drain regions. While the conventional finFET SOI devices provide advantages over MOSFETs formed on bulk semiconductor substrates due to its SOI construction, some fundamental characteristics of the finFET, such as carrier mobility, are the same as those of other MOSFETs because the finFET source, drain and channel regions are typically made from conventional bulk MOSFET semiconductor materials (e.g., silicon).
The fin structure of finFET SOI devices can be located below several different layers, including a photoresist layer, a bottom anti-reflective coating (BARC) layer, and a polysilicon layer. Various problems can exist with such a configuration. The photoresist layer may be thinner over the fin structure. In contrast, the polysilicon layer and BARC layer may be very thick at the edge of the fin structure. Such a configuration leads to large over-etch requirements for the BARC layer and the polysilicon layer. Such requirements increase the size of the transistor.
There is a need for an integrated circuit or electronic device that includes channel regions with higher channel mobility, higher immunity to short channel effects, and higher drive current. Further, there is a need for a method of patterning finFET devices having small critical dimensions. Even further, there is a need for a method of fabricating strained silicon fin-shaped channels for finFET devices. Further still, there is a need for a finFET device with a strained semiconductor fin-shaped channel region. Yet even further, there is a need for a process of fabricating a finFET device with a strained semiconductor fin-shaped channel.